Deep Learning, Neuromorphic Computing & MicroArchitecture · IIT Madras
Efficient, Robust &
Brain-Inspired AI
BrainSeek Lab works across the full stack of modern deep learning and computer architecture — from microarchitecture security and RISC-V based SoC design to adversarial robustness, model compression, spiking neural networks, and neuromorphic hardware.
4+
Publications
13+
GPUs across 3 HPC Clusters
16
Team Members
Focus Areas
What We Work On
Our research spans hardware and software — secure microarchitecture and RISC-V SoC design, algorithmic efficiency, robustness, brain-inspired computing, and efficient language models.
Microarchitecture Security
Investigating side-channel and speculative-execution vulnerabilities at the microarchitecture level, and designing hardware-level mitigations that preserve performance while closing security gaps.
RISC-V Based SoC Design
Building custom RISC-V based systems-on-chip tailored for efficient, secure, and neuromorphic-aware compute — bridging our architecture and hardware accelerator research with open ISA design.
Adversarial Attacks & Defence
Studying how deep learning models fail under adversarial perturbations and building robust defences — from certified defences to empirical hardening of vision and language models.
Model Compression & Quantization
Making neural networks smaller and faster without sacrificing accuracy. We work on pruning, quantization-aware training, and hardware-aware compression for efficient deployment.
Knowledge Distillation
Transferring the knowledge of large teacher models into compact student networks — enabling capable models to run on resource-constrained devices.
Small Language Models
Designing efficient SLMs (including ShisuLM) for constrained environments. We explore architecture choices, training strategies, and distillation techniques for capable small-scale language models.
Spiking Neural Networks
Designing and training SNNs for energy-efficient inference — including ANN-SNN conversion (PASCAL), direct training, and biologically plausible learning rules like Equilibrium Propagation.
Neuromorphic Hardware
Building DL accelerators tailored for sparse, spike-based computation. We exploit dual sparsity (APex) and design quantization schemes for real-time neuromorphic deployment.
Energy Based Models
Exploring energy-based learning frameworks as principled alternatives to standard supervised training — including Equilibrium Propagation as a biologically plausible credit assignment mechanism.
Latest Work
Recent Publications
A selection of recent work from BrainSeek Lab.
2026
DATE 2026
MicroArchitecture Security
SPOILER-GUARD: Gating Latency Effects of Memory Accesses through Randomized Dependency Prediction
SPOILER-GUARD is a hardware defense against transient execution attacks that exploit false dependencies from partial address aliasing (the SPOILER attack). It randomizes the physical address bits used in load-store comparisons, cutting misspeculation to 0.0004% while improving integer/FP performance by 2.12%/2.87%, with minimal hardware overhead. Accepted at DATE 2026
2026
IEEE ISVLSI 2026
Hardware Accelerator
SNN
APEX: A Dual-Sparsity Accelerator for Precise and Efficient SNN Inference
APex is a hardware accelerator design that simultaneously exploits both spatial sparsity (zero activations within a timestep) and temporal sparsity (silent neurons across timesteps) in SNNs, enabling significant energy and compute savings on neuromorphic hardware. Published at IEEE International Symposium on VLSI (ISVLSI).
Devgokul Bawa Venkatesh, Sreeram Radhakrishnan, Rajshekhar Rakshit, Gopalakrishnan Srinivasan
