Research Output

Publications

Peer-reviewed work from BrainSeek Lab spanning microarchitecture security, RISC-V SoC design, neuromorphic computing, spiking networks, and efficient AI

2026

DATE 2026 MicroArchitecture Security

SPOILER-GUARD: Gating Latency Effects of Memory Accesses through Randomized Dependency Prediction

SPOILER-GUARD is a hardware defense against transient execution attacks that exploit false dependencies from partial address aliasing (the SPOILER attack). It randomizes the physical address bits used in load-store comparisons, cutting misspeculation to 0.0004% while improving integer/FP performance by 2.12%/2.87%, with minimal hardware overhead. Accepted at DATE 2026

Gayathri Subramanian, P Girinath, Nitya Ranganathan, Kamakoti Veezhinathan, Gopalakrishnan Srinivasan

2026

IEEE ISVLSI 2026 Hardware Accelerator SNN

APEX: A Dual-Sparsity Accelerator for Precise and Efficient SNN Inference

APex is a hardware accelerator design that simultaneously exploits both spatial sparsity (zero activations within a timestep) and temporal sparsity (silent neurons across timesteps) in SNNs, enabling significant energy and compute savings on neuromorphic hardware. Published at IEEE International Symposium on VLSI (ISVLSI).

Devgokul Bawa Venkatesh, Sreeram Radhakrishnan, Rajshekhar Rakshit, Gopalakrishnan Srinivasan

2025

ICEdge 2025 Energy Based Learning

Scaling Equilibrium Propagation to Deeper Neural Network Architectures

Equilibrium Propagation (EP) is a biologically plausible learning rule that eliminates the need for explicit error backpropagation. This work addresses the key challenge of making EP practical on deeper architectures, narrowing the gap with standard gradient-based training on complex vision benchmarks.

Sankar Vinayak, Gopalakrishnan Srinivasan

2025

ISLPED 2025 Model Inference

QuAKE: Speeding up Model Inference Using Quick and Approximate Kernels for Exponential Non-Linearities

QuAKE introduces fast approximations for exponential-based nonlinearities (Softmax, GELU, Logistic) that are common bottlenecks in Transformer inference. Instead of relying on specialized hardware or lookup tables, it exploits properties of the IEEE-754 floating-point representation itself to compute cheap, accurate approximations of the exponential function. The approach yields measurable inference speedups — 10-35% on server CPUs and 5-45% on other tested hardware without needing extra memory or precomputation.

Sai Kiran Narayanaswami, Gopalakrishnan Srinivasan, Balaraman Ravindran

2025

Transactions on ML Research (TMLR) ANN-SNN Conversion SNN

PASCAL: Precise and Efficient ANN-SNN Conversion using Spike Accumulation and Adaptive Layerwise Activation

SNNs offer energy efficiency over ANNs by replacing multiply-accumulate ops with sparse accumulate ops. PASCAL achieves a mathematically exact ANN-SNN equivalence using a novel spike accumulation scheme and adaptive per-layer quantization of the QCFS activation. ResNet-34 reaches ~74% ImageNet accuracy with a 56× reduction in inference timesteps versus prior methods.

Pranav Ramesh, Gopalakrishnan Srinivasan